Recent advances in silicon cell technologies have reduced the RA of for example, a 30V device from 50 to 14 mOhm-mm2. Advances in semiconductor device technology are likely to continue to reduce the RA. If this trend continues an active area of approximately 10 mm2 can be expected to have an Rdson of 630 μOhm to 240 μOhm depending on the fabrication process.
If semiconductor device technologies are able to meet these target specifications packaging technologies will have to improve significantly. The introduction of DirectFET® technology has enabled significant reductions in die free package resistance compared to conventional 8 lead SOIC power packages. A DirectFET® package (sold by the assignee of the present application), in simple terms, is a semiconductor package which includes a conductive can, and a semiconductor die disposed inside the can and electrically and mechanically connected to an interior surface of the can. U.S. Pat. No. 6,624,522 shows an example of such a package. Using the packaging concept embodied in a DirectFET® package, package resistance, excluding top metal resistance (the resistance associated with the power electrode, e.g. source electrode, of the semiconductor die which is directly connected by solder, conductive epoxy or the like to a conductive pad of a substrate such as a circuit board) is now sub 100 μOhm. However, when one considers the top metal resistance this is increased somewhat to between 0.2 and 0.7 mOhm depending on the model used. For example, through modeling it has been found that the top metallization can include current paths with up to 0.66 mOhm resistance. It is, therefore, desirable to reduce the resistance of the top metal of the semiconductor die in order to improve the overall resistance of a package such as a DirectFET® package.